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general description the MAX9206/max9208 deserializers transform a high- speed serial bus low-voltage differential signaling (blvds) data stream into 10-bit-wide parallel lvcmos/ lvttl data and clock. the deserializers pair with seri- alizers such as the max9205/max9207, which gener- ate a serial blvds signal from 10-bit-wide parallel data. the serializer/deserializer combination reduces interconnect, simplifies pc board layout, and reduces board size. the MAX9206/max9208 receive serial data at 400mbps and 600mbps, respectively, over board traces or twisted-pair cables. these devices combine frequency lock, bit lock, and frame lock to produce a parallel-rate clock and word-aligned 10-bit data. serialization eliminates parallel bus clock-to-data and data-to-data skew. a power-down mode reduces typical supply current to less than 600?. upon power-up (applying power or driving pwrdn high), the MAX9206/max9208 estab- lish lock after receiving synchronization signals or serial data from the max9205/max9207. an output enable allows the outputs to be disabled, putting the parallel data outputs and recovered output clock into a high- impedance state without losing lock. the MAX9206/max9208 operate from a single +3.3v supply and are specified for operation from -40 c to +85 c. the MAX9206/max9208 are available in 28-pin ssop packages. applications features stand-alone deserializer (vs. serdes) ideal for unidirectional links automatic clock recovery allow hot insertion and synchronization without system interruption blvds serial input rated for point-to-point and bus applications fast pseudorandom lock wide reference clock input range 16mhz to 40mhz (MAX9206) 40mhz to 60mhz (max9208) high 720ps (p-p) jitter tolerance (MAX9206) low 30ma supply current (MAX9206 at 16mhz) 10-bit parallel lvcmos/lvttl output up to 600mbps throughput (max9208) programmable output strobe edge pin compatible to ds92lv1212a and ds92lv1224 MAX9206/max9208 10-bit bus lvds deserializers ________________________________________________________________ maxim integrated products 1 19-2130; rev 0; 8/01 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp. range ref clock range (mhz) pin- package MAX9206 eai -40 c to +85 c 16 to 40 28 ssop max9208 eai -40 c to +85 c 40 to 60 28 ssop evaluation kit available pin configuration appears at end of data sheet. pc board or twisted pair tclk pll pll en ren pwrdn input latch parallel-to-serial output latch serial-to-parallel timing and control timing and control clock recovery rclk lock sync 1 sync 2 out+ out- ri+ ri- 100 ? 100 ? tclk_r/f rclk_r/f refclk rout_ in_ 10 10 bus lvds max9205 max9207 MAX9206 max9208 typical operating circuit cellular phone base stations add/drop muxes digital cross-connects dslams network switches and routers backplane interconnect
MAX9206/max9208 10-bit bus lvds deserializers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc , dv cc to agnd, dgnd .................................-0.3v to +4v ri+, ri- to agnd, dgnd .........................................-0.3v to +4v all other pins to dgnd ..............................-0.3v to dv cc + 0.3v rout_ short-circuit duration (note 1) ......................continuous continuous power dissipation (t a = +70 c) 28-pin ssop (derate 9.5mw/ c above +70 c) ..........762mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c esd rating (human body model, ri+, ri-) .........................?kv lead temperature (soldering, 10s) .................................+300 c dc electrical characteristics (av cc = dv cc = +3.0v to +3.6v, differential input voltage | v id | = 0.1v to 1.2v, common-mode voltage v cm = | v id /2 | to 2.4v - | v id /2 | , t a = -40 c to +85 c, unless otherwise noted. typical values are at av cc = dv cc = +3.3v, v cm = 1.1v, | v id | = 0.2v, t a = +25 c.) (notes 2, 3) parameter symbol conditions min typ max units power supply 16mhz 30 45 MAX9206 40mhz 57 75 40mhz 55 75 supply current i cc c l = 15pf, worst-case pattern, figure 1 max9208 60mhz 80 100 ma power-down supply current i ccx pwrdwn = low 1 ma lvcmos/lvttl logic inputs (ren, refclk, rclk_r/ f , pwrdn ) high-level input voltage v ih 2.0 v cc v low-level input voltage v il 0 0.8 v input current i in v in = 0, av cc , or dv cc -15 15 ? lvcmos/lvttl logic outputs (rout_, rclk, lock ) high-level output voltage v oh i oh = -5ma 2.2 2.9 v cc v low-level output voltage v ol i ol = 5ma 0 0.33 0.5 v output short-circuit current i os v rout_ = 0 -15 -38 -85 ma output high-impedance current i oz pwrdn = low, v rout_ = v rclk = v lock = 0, av cc , or dv cc -1 1 a blvds serial input (ri+, ri-) differential input high threshold v th 9 100 mv differential input low threshold v tl -100 -9 mv 0.1v |v id | 0.45v -64 64 input current i ri+ , i ri- 0.45v < |v id | 0.6v -82 82 ? 0.1v |v id | 0.45v, av cc = dv cc = 0 -64 64 power-off input current i ri+off , i ri-off 0.45v < |v id | 0.6v, av cc = dv cc = 0 -82 82 ? input resistor 1 r in1 av cc = dv cc = 3.6v or 0, figure 2 4 k ? input resistor 2 r in2 av cc = dv cc = 3.6v or 0, figure 2 150 k ?
MAX9206/max9208 10-bit bus lvds deserializers _______________________________________________________________________________________ 3 ac electrical characteristics (av cc = dv cc = +3.0v to +3.6v, c l = 15pf, differential input voltage | v id | = 0.15v to 1.2v, common-mode voltage v cm = | v id /2 | to 2.4v - | v id /2 | , t a = -40 c to +85 c, unless otherwise noted. typical values are at av cc = dv cc = +3.3v, v cm = +1.1v, | v id | = 0.2v, t a = +25 c.) (notes 4, 5) parameter symbol conditions min typ max units reference clock timing requirements (refclk) MAX9206 16 40 refclk frequency f rff max9208 40 60 mhz refclk frequency variation rffv -200 200 ppm MAX9206 25 62.5 refclk period t rfcp max9208 16.666 25 ns refclk duty cycle rfdc 30 50 70 % refclk input transition time t rftt 36 ns switching characteristics MAX9206 25 62.5 recovered clock (rclk) period (note 6) t rcp max9208 16.666 25 ns low-to-high transition time t clh figure 3 1.5 3 ns high-to-low transition time t chl figure 3 2 3 ns MAX9206, 40mhz 1.75 x t rc p + 2 1.75 x t rc p + 3.3 1.75 x t rc p + 6.5 deserializer delay t dd figure 4 max9208, 60mhz 1.75 x t rc p + 1.1 1.75 x t rc p + 3.3 1.75 x t rc p + 5.6 ns rout_ data valid before rclk t ros figure 5 0.4 x t rcp 0.5 x t rc p ns rout_ data valid after rclk t roh figure 5 0.4 x t rcp 0.5 x t rc p ns rclk duty cycle t rdc 43 50 57 % output high-to-high impedance delay t hzr c l = 5pf, figure 6 8 ns output low-to-high impedance delay t lzr c l = 5pf, figure 6 8 ns output high-impedance to high-state delay t zhr c l = 5pf, figure 6 6 ns output high-impedance to low-state delay t zlr c l = 5pf, figure 6 6 ns pll lock time (from pwrdn transition high) t dsr1 sync patterns at input; supply and refclk stable; measured from pwrdn transition high to lock transition low; figure 7 (2048 + 42) x t rfcp ns
MAX9206/max9208 10-bit bus lvds deserializers 4 _______________________________________________________________________________________ note 1: short one output at a time. do not exceed the absolute maximum continuous power dissipation. note 2: current into a pin is defined as positive. current out of a pin is defined as negative. voltages are referenced to ground except v th , v tl , and v id , which are differential input voltages. note 3: dc parameters are production tested at t a = +25? and guaranteed by design and characterization over operating temper- ature range. note 4: ac parameters guaranteed by design and characterization. note 5: c l includes scope probe and test jig capacitance. note 6: t rcp is determined by the period of tclk, which is the reference clock of the serializer driving the deserializer. the frequen- cy of tclk must be within ?00ppm of the refclk frequency. ac electrical characteristics (continued) (av cc = dv cc = +3.0v to +3.6v, c l = 15pf, differential input voltage | v id | = 0.15v to 1.2v, common-mode voltage v cm = | v id /2 | to 2.4v - | v id /2 | , t a = -40 c to +85 c, unless otherwise noted. typical values are at av cc = dv cc = +3.3v, v cm = +1.1v, | v id | = 0.2v, t a = +25 c.) (notes 4, 5) parameter symbol conditions min typ max units pll lock time (from start of sync patterns) t dsr2 pll locked to stable refclk; supply stable; static input; measured from start of sync patterns at input to lock transition low; figure 8 42 x t rfcp ns lock high-z to high-state delay t zhlk figure 7 30 ns 16mhz 1300 MAX9206 40mhz 720 40mhz 720 input jitter tolerance t jt figure 9 max9208 60mhz 320 ps
MAX9206/max9208 10-bit bus lvds deserializers pin description pin name function 1, 12, 13 agnd analog ground 2 rclk_r/ f strobe edge select for recovered clock (rclk). lvttl/lvcmos level input. drive rclk_ r/ f high to strobe rout_ on the rising edge of rclk. drive rclk_r/ f low to strobe rout_ on the falling edge of rclk. 3 refclk reference clock for pll. lvttl/lvcmos level input. 4, 11 av cc analog power supply. bypass av cc with a 0.1f and a 0.001f capacitor to agnd. 5 ri+ serial data input. noninverting blvds differential input. 6 ri- serial data input. inverting blvds differential input. 7 pwrdn power down. lvttl/lvcmos level input. drive pwrdn low to stop the pll and put rout_, lock , and rclk in high impedance . 8 ren output enable. lvttl/lvcmos level input. drive ren low to put rout_ and rclk in high impedance. lock remains active, indicating the status of the serial input. 9 rclk recovered clock. lvttl/lvcmos level output. use rclk to strobe rout_. 10 lock lock indicator. lvttl/lvcmos level output. lock goes low when the pll has achieved frequency and phase lock to the serial input, and the framing bits have been identified. 14, 20, 22 dgnd digital ground 15 19, 24 28 rout9 rout0 parallel output data. lvttl/lvcmos level outputs. rout_ is valid on the second selected strobe edge of rclk after lock goes low. 21, 23 dv cc digital power supply. bypass dv cc with a 0.1f and a 0.001f capacitor to dgnd. figure 1. worst-case icc test pattern 0 0 end bit 9 8 7 6 5 4 3 1 0 start bit end bit 9 7 6 5 4 3 2 1 2 1 82 start bit t dd rclk_r/f = high start bit ri rclk odd rout even rout test circuits/timing diagrams _______________________________________________________________________________________ 5
MAX9206/max9208 10-bit bus lvds deserializers figure 5. data valid times t ros t roh rclk rclk_r/f = low rclk rclk_r/f = high data valid before rclk data valid after rclk rout_ 50% 50% figure 6. high-impedance test circuit and timing c l +7v for t lzr and t zlr open for t hzr and t zhr 450 ? 500 ? scope 50 ? ren rout_ rclk v ol v oh t lzr t hzr t zlr 1.5v t zhr v ol +0.5v v oh -0.5v figure 2. input fail-safe circuit v cc v cc - 0.3v to deserializing circuitry ri+ ri- r in1 r in1 r in2 figure 3. lvcmos/lvttl output load and transition times 80% 80% 20% 20% t clh t chl c l 15pf lvcmos/lvttl output figure 4. input-to-output delay start bit start bit end bit start bit end bit symbol n symbol n+1 symbol n-1 symbol n t dd ri rclk rout_ rclk_r/f = high 0123456789 0123456789 012 test circuits/timing diagrams (continued) 6 ______________________________________________________________________________________
MAX9206/max9208 10-bit bus lvds deserializers _______________________________________________________________________________________ 7 t rfcp t rcp data data sync t dd sync patterns 111111 000000 rclk_r/f = low refclk ri lock rclk rout_ pwrdn high-z high-z high-z high-z high-z high-z don't care t hzr or t lzr 42 x t rfcp 2048 x t rfcp t dsr1 (2048 + 42)t rfcp t zhlk figure 7. pll lock time from pwrdn 42t rfcp sync patterns 111111 000000 data data data data t dd t rcp sync rclk_r/f = low refclk ri rclk rout_ lock figure 8. deserializer pll lock time from sync patterns test circuits/timing diagrams (continued)
MAX9206/max9208 10-bit bus lvds deserializers 8 _______________________________________________________________________________________ detailed description the MAX9206/max9208 deserialize a blvds serializ- er's output into 10-bit wide parallel lvcmos/lvttl data and a parallel rate clock. the MAX9206/max9208 include a pll that locks to the frequency and phase of the serial input, and digital circuits that deserialize and deframe the data. the MAX9206/max9208 have high- input jitter tolerance while receiving data at speeds from 160mbps to 600mbps. combination with the max9205/max9207 blvds serializers allows data transmission across backplanes using pc board traces, or across twin-ax or twisted-pair cables. the MAX9206/max9208 deserializers provide a power- saving, power-down mode when pwrdn is driven low. the output enable, ren, allows the parallel data out- puts (rout_) and recovered clock (rclk) to be enabled or disabled while maintaining lock to the serial input. lock , along with rclk, indicates when data is valid at rout_. parallel, deserialized data at rout_ is strobed out on the selected strobe edge of rclk. the strobe edge of rclk is programmable. the falling edge is selected when rclk_r/ f is low and the rising edge is selected when rclk_r/ f is high. the interface may be point-to-point or a heavily loaded bus. the characteristic impedance of the media and connections can range from 100 ? for a point-to-point interface to 54 ? for a heavily loaded bus. a double-ter- minated point-to-point interface uses a 100 ? termina- tion resistor at each end of the interface, resulting in a total load of 50 ? . a heavily loaded bus with a termina- tion as low as 54 ? at each end of the bus (resulting in a total load of 27 ? ) can be driven. a high state bit and a low state bit, added by the blvds serializer, frame each 10 bits of serial data and create a guaranteed transition for clock recovery. the high bit is prepended at the start and the low bit is appended at the end of the 10-bit data. the rising edge formed at the end/start bit boundary functions as an embedded clock. twelve serial bits (10 data + 2 frame) are transmitted by the serializer and received by the deserializer for each 10 bits of data transferred. the MAX9206 accepts a 16mhz to 40mhz reference clock, and receives serial data at 160mbps (10 data bits x 16mhz) to 400mbps (10 data bits x 40mhz). the max9208 accepts a 40mhz to 60mhz reference clock, and receives serial data at a rate of 400mbps to 600mbps. initialization initialize the MAX9206/max9208 before receiving data. when power is applied, with refclk stable and pwrdn high, rclk and rout_ are held in high impedance, lock goes high, and the on-chip pll locks to refclk in 2048 cycles. after locking to ref- clk, rout_ is active, rclk tracks refclk, and lock remains high. if transitions are detected at the serial input, the pll locks to the phase and frequency of the serial input, finds the frame bits, and drives lock low. if the serial input is sync patterns, lock goes low in 42 or fewer cycles of rclk. when lock goes low, rclk switches from tracking refclk to tracking the serializer reference clock (tclk). deserialized data at rout_ is valid on the second selected strobe edge of rclk after lock goes low. initialization restarts when power is cycled or on the ris- ing edge of pwrdn . lock to pseudorandom data the MAX9206/max9208 lock to pseudorandom serial input data by deductively eliminating rising edges due to data until the embedded end/start edge is found. the end/start edge is identified unless the data con- tains a permanent, consecutive, frame-to-frame rising edge at the same bit position. send sync patterns to guarantee lock. a sync pattern is six consecutive ones followed by six consecutive zeros, repeating every rclk period with only one rising edge (at the end/start boundary). the max9205/max9207 serializers gener- ate sync patterns when sync1 or sync2 is driven high. since sending sync patterns to initialize a deserializer disrupts data transfer to all deserializers receiving the same serial input (figure 11, for example), lock to pseudorandom data is preferred in many applications. lock to pseudorandom data allows initialization of a deserializer after hot insertion without disrupting data communication on other links. the MAX9206/max9208s deductive algorithm pro- vides very fast pseudorandom data lock times. table 1 compares typical lock times for pseudorandom and sync pattern inputs. power-down drive pwrdn low to enter the power-down mode. in power-down, the pll is stopped and the outputs (rout_, rclk, and lock ) are put in high impedance, disabling drive current and also reducing supply cur- rent. output enable when the deserializer is initialized and ren is high, rout_ is active, rclk tracks the serializer reference clock (tclk), and lock is low. driving ren low dis- ables the rout_ and rclk output drivers and does not affect state machine timing. rout_ and rclk go
MAX9206/max9208 10-bit bus lvds deserializers _______________________________________________________________________________________ 9 into high impedance but lock continues to reflect the status of the serial input. driving ren high again enables the rout_ and rclk drivers. losing lock on serial data if one embedded clock edge (rising edge formed by end/start bits) is not detected, lock goes high, rclk tracks refclk, and rout_ stays active but with invalid data. lock stays high for a minimum of two rclk cycles. then, if transitions are detected at the serial input, the pll attempts to lock to the serial input. when the pll locks to serial input data, lock goes low, rclk tracks the serializer reference clock (tclk), and rout_ is valid on the second selected strobe edge of rclk after lock goes low. a minimum of two embedded clock edges in a row are required to regain lock to the serial input after lock goes high. for automatic resynchronization, lock can be con- nected to the max9205/max9207 serializer sync1 or sync2 input. with this connection, when lock goes high, the serializer sends sync patterns until the deseri- alizer locks to the serial input and drives lock low. input fail-safe when the serial input is undriven (a disconnected cable or serializer output in high impedance, for example) an on-chip fail-safe circuit (figure 2) drives the serial input high. the response time of the fail-safe circuit depends on interconnect characteristics. with an undriven input, lock may switch high and low until the fail-safe circuit takes effect. the undriven condition of the link can be detected in spite of lock switching since lock is high long enough to be sampled ( lock is high for at least two rclk cycles after a missed clock edge and rclk keeps running, allowing sampling). if it is required that lock remain high for an undriven input, the on-chip fail-safe circuit can be supplemented with external pullup bias resistors. deserializer jitter tolerance the t jt parameter specifies the total zero-to-peak input jitter the deserializer can tolerate before a sampling error occurs (figure 9). zero-to-peak jitter is measured from the mean value of the deterministic jitter distribu- tion. sources of jitter include the serializer (supply noise, reference clock jitter, pulse skew, and intersym- bol interference), the interconnect (intersymbol interfer- ence, crosstalk, within-pair skew, ground shift), and the deserializer (supply noise). the sum of the zero-to-peak individual jitter sources must be less than or equal to the minimum value of t jt . for example, at 40mhz, the max9205 serializer has 140ps (p-p) maximum deterministic output jitter. the zero-to-peak value is 140ps/2 = 70ps. if the intercon- nect jitter is 100ps (p-p) with a symmetrical distribution, the zero-to-peak jitter is 50ps. the MAX9206 deserializ- er jitter tolerance is 720ps at 40mhz. the total zero-to- peak input jitter is 70ps + 50ps = 120ps, which is less than the jitter tolerance. in this case, the margin is 720ps - 120ps = 600ps. refclk frequency 16mhz 35mhz 40mhz 40mhz data pattern pseudorandom data pseudorandom data pseudorandom data sync patterns maximum 0.749s 0.375s 0.354s 0.134s maximum (clock cycles) 11.99 13.14 14.18 5.37 average 0.318s 0.158s 0.144s 0.103s average (clock cycles) 5.09 5.52 5.76 4.11 minimum 0.13s 0.068s 0.061s 0.061s minimum (clock cycles) 2.08 2.37 2.44 2.45 table 1. typical lock times note: pseudorandom lock performed with 2 15 -1 prbs pattern, 10,000 lock time tests.
MAX9206/max9208 10-bit bus lvds deserializers applications information power-supply bypassing bypass each supply pin with high-frequency surface- mount ceramic 0.1f and 0.001f capacitors in paral- lel as close to the device as possible, with the smaller valued capacitor the closest to the supply pin. differential traces and termination trace characteristics affect the performance of the MAX9206/max9208. use controlled-impedance media. avoid the use of unbalanced cables such as ribbon or simple coaxial cable. balanced cables such as twisted pair offer superior signal quality and tend to generate less emi due to canceling effects. balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. eliminate reflections and ensure that noise couples as common mode by running differential traces close together. reduce skew by matching the electrical length of the traces. excessive skew can result in a degradation of magnetic field cancellation. maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. avoid 90 turns and minimize the number of vias to fur- ther prevent impedance discontinuities. 100 ? parallel data out parallel data in MAX9206 max9208 max9205 max9207 100 ? serialized data figure 10. double-termination point-to-point 100 ? 100 ? asic asic asic 100 ? 100 ? max9205 max9207 max9150 repeater MAX9206 max9208 MAX9206 max9208 figure 11. point-to-point broadcast using max9150 repeater t jt t jt v id = 150mv t rcp /12 figure 9. input jitter tolerance 10 _____________________________________________________________________________________
MAX9206/max9208 10-bit bus lvds deserializers ______________________________________________________________________________________ 11 topologies the MAX9206/max9208 deserializers can operate in a variety of topologies. examples of double-terminated point-to-point and point-to-point broadcast are shown in figures 10 and 11. use 1% surface-mount termina- tion resistors. a point-to-point interface terminated at each end in the characteristic impedance of the cable or pc board traces is shown in figure 10. the total load seen by the serializer is 50 ? . the double termination typically reduces reflections compared to a single 100 ? termi- nation. a single 100 ? termination at the deserializer input is feasible and makes the differential signal swing larger. a point-to-point version of a multidrop bus is shown in figure 11. the low-jitter max9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. compared to a bus, more interconnect is traded for robust hot-plug capability. the repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer con- nections. since repeater jitter is a component of the total jitter seen at the deserializer input (along with other sources of jitter), a low-jitter repeater is essential in most high data-rate applications. board layout a four-layer pc board providing separate power, ground, and signal layers is recommended. keep the lvttl/lvcmos inputs and outputs separated from the blvds inputs to prevent coupling into the blvds lines. chip information transistor count: 9602 process: cmos logic inputs ren pwrdn conditions outputs x low power applied and stable power-down mode. pll is stopped. current consumption is reduced to 400a (typ). rout_, rclk, and lock are high impedance. low high deserializer initialized rclk and rout_ are high impedance. lock is active, indicating the serial input status. high high deserializer initialized rclk and rout_ are active. lock is active, indicating the serial input status. table 2. input/output function table x = don t care 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rout0 rout1 rout2 rout3 rout4 dv cc rout9 dgnd dv cc dgnd rout5 rout6 rout7 rout8 dgnd agnd agnd av cc lock rclk ren pwrdn ri- ri+ av cc refclk rclk_r/f agnd ssop top view MAX9206/ max9208 pin configuration
MAX9206/max9208 10-bit bus lvds deserializers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information ssop.eps

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